“Optimization of breakdown voltage and on-state performance of silicon and wide bandgap power semiconductor devices”

Dept: Electrical & Computer Engineering

Chair: Petru Andrei, Ph.D.

Abstract

Power semiconductor devices for medium and high voltage applications are fundamentally constrained by the coupled requirements of sustaining high breakdown voltages and low specific on-state resistance, constraints that are governed by the full spatial structure of the doping profile rather than by a few scalar design parameters. This dissertation develops a rigorous adjoint-based optimization framework in which the drift–diffusion model is used to derive functional sensitivities of breakdown voltage, on-state current, and on-state resistance with respect to the local doping concentration at each node of a large-scale finite element mesh, thereby enabling gradient-based updates in a design space with more than 104 control variables. These sensitivities are embedded into a unified numerical scheme that accommodates unconstrained, constrained, and weighted multi-objective formulations, including cases in which breakdown voltage is maximized subject to an upper bound on on-state resistance, on-state resistance is minimized at a prescribed breakdown voltage, or both figures of merit are optimized simultaneously under device-level constraints. The methodology is first instantiated for silicon power MOSFET and IGBT structures, where it is shown to systematically reshape the doping profiles in the drift and channel regions, yielding measurable improvements in breakdown voltage and on-state characteristics relative to baseline designs. The same framework is then extended to a 1.2 kV 4H SiC MOSFET using temperature and doping-dependent models for bandgap, mobility, and recombination, thereby elucidating how optimal doping distributions and attainable figures of merit differ between silicon and wide bandgap technologies. Collectively, these results demonstrate that adjoint-based large-scale optimization provides a mathematically rigorous and computationally tractable pathway toward approaching material-imposed performance limits in next-generation power semiconductor devices.