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DSP with FPGAs: Xilinx  HDL Manual  4/e  ISBN 0-9755494-6-4   Download free PDF here

45 VHDL and 44 Verilog Vivado projects from the DSP with FPGAs book 4/e

250 source files in the VHDL folder and 420 files in the Verilog folder

 

My Link-Tips:

My book home dsp4fpgas.htm

DSP with FPGAs link list dsp4fpga.htm
Obfuscation in C, VHDL and Verilog tutorial o4.htm

C2H on DE2 tutorial C2HonDE2.htm

LISA RISC link list lisa.htm

CSE source cse.htm

CMAG source cmag.htm

My Faculty home page https://www.eng.famu.fsu.edu/ece/people/meyer-baese  

My CCLI project page http://www.eng.fsu.edu/~umb

Springer Verlag order  http://www.springer.com/engineering/signals/book/978-3-540-72612-8

Amazon book order  http://www.amazon.com

 

 VHDL LABORATORY new 2012

Lab 1: DSP with DE2
lab1.pdf (198.684 KB)

DE2_lab1.zip (19.984 KB)

Lab1KeyUwe.sof (821.391 KB)

Lab 2: Number Systems and Quantization
lab2.pdf (114.577 KB)

DE2_lab2.zip (14.898 KB)

lab2keyUwe.sof (821.396 KB)
 

Lab 3: Signal + Systems
lab3.pdf (54.677 KB)

Lab 4 M-Files
DE2_pin_small.csv (8.113 KB)

lab4.pdf (214.496 KB)

fungen.m (1.089 KB)

Lab4KeyUwe.sof (821.391 KB)

Lab 5 FIR filter
lab5.pdf (98.444 KB)

DE2_pin_small.csv (8.113 KB)

f5direct.vhd (1.873 KB)

Lab5keyUwe.sof (821.391 KB)
 

Lab 6 IIR Filter
lab6.pdf (86.853 KB)

Lab6KeyUwe.sof (821.391 KB)

setup_iir3.m (0.487 KB)

Lab7 DFT
lab7.pdf (149.658 KB)

bf0.vhd (1.313 KB)

bf1.vhd (1.521 KB)

Lab7KeyUwe.sof (821.391 KB)

fun4fft.m (1.083 KB)

seg7_BAR.vhd (1.603 KB)

Lab 8 Intellectual Property
ug_fir_compiler.pdf (1.919 MB)

ug_fft.pdf (1.045 MB)

f5.dat (0.042 KB)

lab8.pdf (151.678 KB)
 

 

 

 SIMULINK LABORATORY

Lab Intr. to Simulink and DSP Builder
lab1.mdl (29.062 Kb)
lab1inc.mdl (22.109 Kb)
Download instructions here (179.933 Kb)

Lab 2: Number Systems and Quantization
Download instructions here (76.718 Kb)
 

Lab 3 Signal Flow Graphs
Download instructions here (111.199 Kb)
sfg.mdl (23.749 Kb)

Lab 4 M-Files
funcgen.m(0.599 Kb)
Download instructions here (158.417 Kb)

Lab 5 FIR filter
F5direct.mdl (32.597 Kb)
F5transposed.mdl (29.586 Kb)
Lab FIR instructions (108.701 Kb)
maf.mdl (22.732 Kb)
showfft.m (0.233 Kb)
 

Lab 6 IIR Filter
IIRorder1.mdl (27.839 Kb)
IIRorder3.mdl (30.286 Kb)
Download instructions here (144.678 Kb)
setup_iir3.m (0.425 Kb)
showfft.m (0.229 Kb)

Lab7 DFT
goertzel.mdl (60.325 Kb)

goertzel8.m (0.34 Kb)
Download instructions here (126.523 Kb)

Lab 8 FFT
dif8.mdl (91.51 Kb)
Download instructions here (99.227 Kb)
 

 

 

 SIMULINK LABORATORY

Lab Intr. to Simulink and Xilinx System Generator
lab1.mdl (106.902 Kb)
lab1.ucf (1.235 Kb)
lab1inc.mdl (96.096 Kb)
Lab Intro Simulink.pdf (337.067 Kb)

Lab 2: Number Systems and Quantization
Download instructions here (295.574 Kb)
 

Lab 3 Signal Flow Graphs
Download instructions here (207.118 Kb)
sfg.mdl (28.701 Kb)

Lab 4 M-Files
funcgen.m (0.592 Kb)
Download instructions here (276.306 Kb)

Lab 5 FIR filter
F5direct.mdl (60.316 Kb)
F5transposed.mdl (49.778 Kb)
Download instructions here (604.687 Kb)
maf.mdl (44.351 Kb)
showfft.m (0.233 Kb)
 

Lab 6 IIR Filter
IIRorder1.mdl (33.618 Kb)
IIRorder3.mdl (41.562 Kb)
Download instructions here (232.401 Kb)
setup_iir3.m (0.425 Kb)
showfft.m (0.229 Kb)

Lab7 DFT
goertzel.m (0.34 Kb)
Goertzel.mdl (39.857 Kb)
Download instructions here (211.167 Kb)

Lab 8 FFT
Lab8.mdl (99.282 Kb)
Download Instructions here (183.75 Kb)
 

 

 

Xilinx/Digilent Nexys demo:

Matlab file:                Nexys_AD_DA.mdl

UCF file:                    Nexys.ucf

Prog. file:                   nexys_ad_da_clk_wrapper.bit

QuckTimeVideo:       NexysDemo.MOV

Flash Video:               NexysDemo.flv

Movie text:                 Nexys.html

 

Articulate demos:

Getting Started Quiz : quiz.html

PPT Sound Demo:        player.html

 

RELATED PUBLICATIONS*

 

Uwe Meyer-Baese, A. Vera, A. Meyer-Baese, M. Pattichis, R. Perry, “Discrete Wavelet Transform FPGA Design using MatLab/Simulink,” Proc. SPIE Int. Soc. Opt. Eng., April 2006, Vol. 6247, pp. 624703-1-10. Download PDF file here

 

U. Meyer-Baese, A. Vera, A. Meyer-Baese, M. Pattichis, R. Perry, “Smart Altera Firmware for DSP with FPGAs,” Proc. SPIE Int. Soc. Opt. Eng., April 2007, Vol. 6576, pp. 65760T-1-11 Download PDF file here

 

Uwe Meyer-Baese, A. Vera, A. Meyer-Baese, M. Pattichis, R. Perry, “DSP with FPGAs: a Xilinx/Simulink-based course and laboratory,” Proc. SPIE Int. Soc. Opt. Eng., March 2008, Vol. 6979, pp.  Download PDF file here

 

Presenter in bold

 

*Copyright 2006, 2007, 2008 Society of Photo-Optical Instrumentation Engineers. These papers were published in SPIE conference Proceedings and are made available as an electronic reprint (preprint) with permission of SPIE. One print or electronic copy may be made for personal use only. Systematic or multiple reproduction, distribution to multiple locations via electronic or other means, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.

 

 

ACKNOLEGMENT:           This material is based upon work supported by the National Science Foundation under Grant No. DUE-0442600." Products and company name used may be trademarks of their respective owners. The authors would like to thanks Altera and Xilinx for the provided hardware and software under the University programs. Any opinions, findings, and conclusions or recommendations expressed in this webpage are those of the authors and do not necessarily reflect the views of the sponsors.